Japanese Patent Application Publication 2001-352707 discloses a semiconductor apparatus in which an LDMOS (Lateral Diffused Metal Oxide Semiconductor) transistor element is formed on a surface part of a semiconductor substrate.
A semiconductor apparatus 80 disclosed in JP-A-2001-352707 is described below with reference to FIG. 11. The semiconductor apparatus 80 is formed with using a SOI (silicon on insulator) substrate that includes a P type silicon substrate 2, an insulating layer 3, an N type layer 1. In the semiconductor apparatus 80, an N type region 6 (i.e., a drift region 6) is disposed so that the drift region 6 surrounds an N+ type drain region 5. The N type region has higher concentration than the N type layer 1. Concentration in the drift region 6 becomes higher as closer to the N+ type drain region 5. A P+ type contact region 9 is adjacent to and adjoins an N+ type source region 8. The P+ type contact region 9 extends so as to cover a part of the bottom side of the N+ type source region 8. A LOCOS (Local Oxidation of Silicon) oxide layer 4 and a gate electrode 11 are shown in FIG. 11.
The semiconductor apparatus 80 shown in FIG. 11 includes an LDMOS transistor element. A source and a drain of the LDMOS transistor element are disposed in a surface layer of the N type layer 1. Carrier flow direction is lateral. Since the LDMOS transistor element is capable of being switched at higher speed compared to other switching elements, the LDMOS transistor element may be utilized in a switching circuit, a switching power supply unit and the like, in which a switching element is switched on and off at high speed.
Generally, such a switching circuit as a DC-DC converter and an inverter is operated at a higher operating frequency, and thus, required inductance and capacitance are small. In the above case, it may be possible to configure a smaller switching circuit in accordance with the required smaller inductance and capacitance. Therefore, a transistor having a high speed switching capability is desired, and the LDMOS transistor element may be suitable. However, in general, when a transistor (including the LDMOS transistor element) is switched at high speed, a rapid voltage change causes a drain voltage overshoot (i.e., surge voltage), and accordingly, strong noise (ringing) generation and switching loss are caused.
Japanese Patent Application Publication 2004-6598, corresponding to U.S. Pat. No. 6,700,156, discloses a semiconductor apparatus associated with a transistor element used for a switching circuit.
A semiconductor apparatus 90 disclosed in JP-A-2004-6598 is described below with reference to FIG. 12. The semiconductor apparatus 90 is a sort of a VDMOS (Vertical Diffused Metal Oxide Semiconductor) transistor element. A gate and a source of the device 90 are disposed in both sides of a semiconductor substrate, respectively. The carrier flow direction is vertical. The semiconductor apparatus 90 shown in FIG. 12 is characterized by a P type layer 14. The P type layer 14 is adjacent to a P type base layer 12, and includes low-concentrated P-conductivity-type impurities. A conductivity type of the P type layer 14 is opposite to that of a drain.
In the semiconductor apparatus 90 shown in FIG. 12, as a drain voltage is higher, a gate-to-drain capacitance increases due to existence of the P-type layer 14. As a result, a surge voltage generation in the drain is suppressed. The P-type layer effectively functions in the VDMOS structured semiconductor apparatus 90. However, when a layer like the P-type layer 14 is disposed in a LDMOS structured semiconductor device, it is difficult to design a LDMOS semiconductor device due to its large influence on a carrier channel. Moreover, in the semiconductor apparatus 90, a flow of carriers through the low-impurity concentration P-type layer 14 causes a larger on-state resistance. Furthermore, only the existence of the P-type layer 14 may not sufficiently increase the gate-to-drain capacitance, and may not sufficiently suppress the surge voltage generation.